Developments in semiconductor technologies over the last few years have allowed the Figure of Merit (FoM) and circuit efficiency to be maintained, or even in some cases improved, as the size of a semiconductor device continually shrinks. This means that a modern integrated circuit device (e.g., chip die or power semiconductor device) generally has a lesser connection area (or footprint) than earlier generations of dice, and it has a much greater effective power density per given area. This also means that thermal loading over a given area also has increased.
Exemplary semiconductor technologies that use a shrinking form factor include embedded die and packaging technologies. In one example, an integrated circuit (IC) chip die may be located within a core layer of a printed circuit board (PCB), or between layers of a multi-layer circuit board. This technique frees up surface area on the PCB layer surfaces for other circuit components. Thus, more components resulting in greater application feature sets may be contained within a smaller package. Heat management of the die within the PCB is important for predictable circuit performance and to prolong the life of the semiconductor device and associated packaging and circuit topology, particularly when considering increases in thermal loading.